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The
register has no effect unless the core is idled. The bits in this
SIC_IWR
register correspond to those of the System Interrupt Mask (
and Interrupt Status (
After reset, all valid bits of this register are set to 1, enabling the wakeup
function for all interrupts that are not masked. Before enabling interrupts,
configure this register in the reset initialization sequence. The
register can be read from or written to at any time. To prevent spurious or
lost interrupt activity, this register should be written to only when all
peripheral interrupts are disabled.
Note the wakeup function is independent of the interrupt mask
function. If an interrupt source is enabled in
off in
SIC_IMASK
generate an interrupt.
For a listing of the default System Interrupt Wakeup-Enable register set-
tings, refer to the System Interrupt Appendix of the Blackfin Processor
Hardware Reference for your part.
SIC_ISR Register
The System Interrupt Controller (SIC) includes a read-only status regis-
ter, the System Interrupt Status register (
Interrupt Appendix of the Blackfin Processor Hardware Reference for your
part. Each valid bit in this register corresponds to one of the peripheral
interrupt sources. The bit is set when the SIC detects the interrupt is
asserted and cleared when the SIC detects that the peripheral interrupt
input has been deasserted. Note for some peripherals, such as programma-
ble flag asynchronous input interrupts, many cycles of latency may pass
from the time an interrupt service routine initiates the clearing of the
interrupt (usually by writing a system MMR) to the time the SIC senses
that the interrupt has been deasserted.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
) registers.
SIC_ISR
, the core wakes up if it is idled, but it does not
Program Sequencer
SIC_IWR
), shown in the System
SIC_ISR
)
SIC_IMASK
SIC_IWR
but masked
4-35
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