Analog Devices ADSP-BF53x Blackfin Reference page 454

Instruction Overview
Modified Type I LFSR (without feedback)
Two instructions support the
Dreg_lo = CC = BXORSHIFT(A0, dreg)
Dreg_lo = CC = BXOR(A0, dreg)
In the first instruction the Accumulator
XOR reduction. This instruction provides a bit-wise XOR of
AND'ed with a
flag and the least significant bit of the destination register. The operation
is shown in Figure
The upper 15 bits of
after the operation.
Before XOR Reduction
A0[39]
XOR Reduction
0
A0[38]
After Operation
dr[15]
Figure 12-2. A0 Left-Shifted by 1 Followed by XOR Reduction
12-12 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
LSFR
. The result of the operation is placed into both the
dreg
12-2.
are overwritten with zero, and dr[0] = IN
dreg_lo
A0[38] A0[37]
A0[39:0]
+
D[31]
A0[30]
dr[14] dr[13]
dreg_lo[15:0]
with no feedback.
is left-shifted by 1 prior to the
A0
A0[0]
+ + +
IN
D[2] D[1] D[0]
A0[1] A0[0]
IN
logically
A0
CC
0
Left Shift by 1
CC dreg_lo
0