Table of Contents
Advertisement
The Type I
LFSR
40-bit state residing in Accumulator
reduction operation. The result is placed in CC and a destination register
half.
The Type I
LFSR
to a 40-bit state residing in
In the following circuits describing the BXOR instruction group, a
bit-wise XOR reduction is defined as:
( (
( (
B (
Out
=
where B
through B
0
contents of Accumulator
32-bit register. The instruction descriptions are shown in
Figure 12-1. Bit-Wise Exclusive-OR Reduction
In the figure above, the bits
with bits D[0] and D[1]. The result from this operation is XOR reduced
according to the following formula.
( )
(
A0 0 [ ]&D 0 [ ] )
s D
=
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
s (no feedback) applies a 32-bit registered mask to a
s (with feedback) applies a 40-bit mask in Accumulator
. The result is shifted into
A0
⊕
)
⊕
)
⊕
B
B
B
0
1
2
represent the N bits that result from masking the
N–1
with the polynomial stored in either
A0
D[0]
A0[0]
A0[1]
bit 0 and
A0
⊕
(
A0 1 [ ]&D 1 [ ]
Logical Operations
, followed by a bit-wise XOR
A0
)
⊕
)
⊕
)
...
B
3
n 1
–
s(D)
D[1]
bit 1 are logically AND'ed
A0
)
A1
.
A0
or a
A1
Figure
12-1.
12-11
Advertisement
Table of Contents
