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Table C-21. Vector Operations Instructions (Sheet 29 of 33)
Instruction
and Version
Vector Multiply and
Multiply-Accumulate
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = (A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi)
Vector Multiply and
Multiply-Accumulate
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = (A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi) (FU)
Vector Multiply and
Multiply-Accumulate
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = (A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi) (IS)
Vector Multiply and
Multiply-Accumulate
Dreg_even = (A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi) ,
A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi
Vector Multiply and
Multiply-Accumulate
Dreg_even = (A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi) ,
A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi (FU)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 0 0 0 0 0 0 0 1 1 op1
0xC00C 0000—
0xC00F DFFF
Dreg
half 1 0 op0
1 1 0 0 0 0 0 0 1 0 0 0 1 1 op1
0xC08C 0000—
0xC08F DFFF
Dreg
half 1 0 op0
1 1 0 0 0 0 0 1 0 0 0 0 1 1 op1
0xC10C 0000—
0xC10F DFFF
Dreg
half 1 0 op0
1 1 0 0 0 0 0 0 0 0 0 0 1 0 op1
0xC008 2000—
0xC00B FFFF
Dreg
half 1 1 op0
1 1 0 0 0 0 0 0 1 0 0 0 1 0 op1
0xC088 2000—
0xC08B FFFF
Dreg
half 1 1 op0
Instruction Opcodes
Bin
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
C-135
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