Analog Devices ADSP-BF53x Blackfin Reference page 662

Instruction Overview
Table 18-14. Options for Quad 8-Bit Average – Byte (Cont'd)
Option
(R)
(T, R)
In the optional reverse source order case (for example, using the (R) syn-
tax), the only difference is the source registers swap places within the
register pair in their byte ordering. Assume a source register pair contains
the data shown in
Table 18-15. I-register Bits and the Byte Alignment
The bytes selected are
Two LSB's of I0 or I1
00b:
01b:
10b:
11b:
The mnemonic derives its name from the fact that the operands are bytes,
the result is one word, and the basic arithmetic operation is "plus" for
addition. The single destination register indicates that averaging is
performed.
18-22 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Description
Reverses the order of the source registers within each register pair. Typical
high performance applications cannot afford the overhead of reloading
both register pair operands to maintain byte order for every calculation.
Instead, they alternate and load only one register pair operand each time
and alternate between the forward and reverse byte order versions of this
instruction. By default, the low order bytes come from the low register in
the register pair. The (R) option causes the low order bytes to come from
the high register.
Combines both of the above options.
Table 18-15.
src_reg_pair_LO
byte7 byte6 byte5
byte5
byte6 byte5
src_reg_pair_HI
byte4 byte3 byte2
byte3 byte2
byte4 byte3 byte2
byte4 byte3 byte2
byte4 byte3
byte1 byte0
byte1 byte0
byte1