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Instruction Overview
Table 15-2. Multiply 16-Bit Operands Options (Cont'd)
Option
Description for
Register Half Destination
(ISS2)
Signed integer with scaling. Multiply
16.0 * 16.0 to produce 32.0 results. No
shift correction. Extract the lower 16
bits. Shift them one place to the left
(multiply x 2). Saturate the result for
16.0 format in destination register half.
Result is between minimum -2
maximum 2
between minimum 0x8000 and maxi-
mum 0x7FFF).
(IH)
Signed integer, high word extract. Mul-
tiply 16.0 * 16.0 to produce 32.0
results. No shift correction. Round 32.0
format value at bit 16. (RND_MOD
bit in the ASTAT register controls the
rounding.) Saturate to 32.0 result.
Extract the upper 16 bits of that value
to the destination register half. Result is
between minimum -2
15
2
-1 (or, expressed in hex, between
minimum 0x8000 and maximum
0x7FFF).
(M)
Mixed mode multiply (valid only for MAC1). When issued in a fraction mode
instruction (with Default, FU, T, TFU, or S2RND mode), multiply 1.15 * 0.16 to
produce 1.31 results.
When issued in an integer mode instruction (with IS, ISS2, or IH mode), multiply
16.0 * 16.0 (signed * unsigned) to produce 32.0 results.
No shift correction in either case. Src_reg_0 is the signed operand and Src_reg_1 is
the unsigned operand.
All other operations proceed according to the other mode flag or Default.
15-48
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
15
and
15
-1 (or, expressed in hex,
15
and maximum
Description for
32-Bit Register Destination
Signed integer with scaling. Multiply
16.0 * 16.0 to produce 32.0 results. No
shift correction. Shift the results one
place to the left (multiply x 2). Saturate
result to 32.0 format. Copy to destina-
tion register. Results range between min-
imum -1 and maximum 2
The resulting hexadecimal range is mini-
mum 0x8000 0000 through maximum
0x7FFF FFFF.
Not applicable.
31
-1.
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