Analog Devices ADSP-BF53x Blackfin Reference page 852

Shift / Rotate Operations Instructions
Table C-16. Shift / Rotate Operations Instructions (Sheet 7 of 9)
Instruction
and Version
Logical Shift
Dreg = Dreg >> uimm5
Logical Shift
Dreg = Dreg << uimm5
Logical Shift
A0 = A0 >> uimm5
Logical Shift
A0 = A0 << uimm5
Logical Shift
A1 = A1 >> uimm5
Logical Shift
A1 = A1 << uimm5
Logical Shift
Dreg <<= Dreg
Logical Shift
Dreg >>= Dreg
C-52 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC682 8100— 1 1 0 0 0 1 1 0 1 x x 0 0 0 1 0
0xC682 8FFF
1 0 0 0 Dest.
0xC682 8000— 1 1 0 0 0 1 1 0 1 x x 0 0 0 1 0
0xC682 8EFF
1 0 0 0 Dest.
0xC683 4100— 1 1 0 0 0 1 1 0 1 x x 0 0 0 1 1
0xC683 41F8
0 1 0 0 0 0 0 2's comp of
0xC683 4000— 1 1 0 0 0 1 1 0 1 x x 0 0 0 1 1
0xC683 40F8
0 1 0 0 0 0 0 uimm5
0xC683 5100— 1 1 0 0 0 1 1 0 1 x x 0 0 0 1 1
0xC683 51F8
0 1 0 1 0 0 0 2's comp of
0xC683 5000— 1 1 0 0 0 1 1 0 1 x x 0 0 0 1 1
0xC683 50F8
0 1 0 1 0 0 0 uimm5
0x4080— 0 1 0 0 0 0 0 0 1 0 Source
0x40BF
0x4040— 0 1 0 0 0 0 0 0 0 1 Source
0x407F
Bin
2's comp. of
Dreg # uimm5
uimm5
Dreg #
uimm5
uimm5
Dreg #
Dreg #
Source
Dreg #
Source
Dreg #
0 0 0
0 0 0
0 0 0
0 0 0
Dest.
Dreg #
Dest.
Dreg #