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Core Interrupt Pending Register (IPEND)
RO. For all bits except bit 4, 0 - No interrupt pending, 1 - Interrupt pending or active
0xFFE0 2108
15 14 13 12 11 10
IVG15
IVG14
IVG13
IVG12
IVG11
IVG10
IVG9
Figure 4-7. Core Interrupt Pending Register
Event Vector Table
The Event Vector Table (EVT) is a hardware table with sixteen entries
that are each 32 bits wide. The EVT contains an entry for each possible
core event. Entries are accessed as MMRs, and each entry can be pro-
grammed at reset with the corresponding vector address for the interrupt
service routine. When an event occurs, instruction fetch starts at the
address location in the EVT entry for that event.
The processor architecture allows unique addresses to be programmed into
each of the interrupt vectors; that is, interrupt vectors are not determined
by a fixed offset from an interrupt vector table base address. This approach
minimizes latency by not requiring a long jump from the vector table to
the actual ISR code.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31 30 29 28 27 26
25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
9
8
0
0
0
0
0
0
0
0
Program Sequencer
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
EMU (Emulation)
RST (Reset)
NMI (Nonmaskable Interrupt)
EVX (Exception)
Global Interrupt Disable
IVHW (Hardware Error)
IVTMR (Core Timer)
IVG7
IVG8
Reset = 0x0000 0010
0 - Interrupts globally enabled
1 - Interrupts globally disabled
Set and cleared by Event Con-
troller only
4-41
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