Analog Devices ADSP-BF53x Blackfin Reference page 913

Table C-21. Vector Operations Instructions (Sheet 7 of 33)
Instruction
and Version
Vector Add / Subtract
Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg (CO, ASL)
Vector Add / Subtract
Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg (SCO)
Vector Add / Subtract
Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg (SCO, ASR)
Vector Add / Subtract
Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg (SCO, ASL)
Vector Add / Subtract
Dreg = Dreg + Dreg, Dreg = Dreg – Dreg
Vector Add / Subtract
Dreg = Dreg + Dreg, Dreg = Dreg – Dreg (S)
Vector Add / Subtract
Dreg = A1 + A0, Dreg = A1 – A0
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 1 0 x x x 1 0 0 0 0 1
0xC421 D000—
0xC421 DFFF
1 1 0 1
1 1 0 0 0 1 0 x x x 1 0 0 0 0 1
0xC421 3000—
0xC421 3FFF
0 0 1 1
1 1 0 0 0 1 0 x x x 1 0 0 0 0 1
0xC421 B000—
0xC421 BFFF
1 0 1 1
1 1 0 0 0 1 0 x x x 1 0 0 0 0 1
0xC421 F000—
0xC421 FFFF
1 1 1 1
1 1 0 0 0 1 0 x x x 0 0 0 1 0 0
0xC404 8000—
0xC404 8FFF
1 0 0 0
1 1 0 0 0 1 0 x x x 0 0 0 1 0 0
0xC404 A000—
0xC404 AFFF
1 0 1 0
1 1 0 0 0 1 0 x x x 0 1 0 0 0 1
0xC411 003F—
0xC411 0FC0
0 0 0 0
Instruction Opcodes
Bin
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0
Dreg # Dreg # 1 1 1 1 1 1
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
C-113