Load Low Data Register Half - Analog Devices ADSP-BF53x Blackfin Reference

Load Low Data Register Half

General Form
Dreg_lo = W [ indirect_address ]
Syntax
Dreg_lo = W [ Ireg ] ;
Dreg_lo = W [ Ireg ++ ] ;
addressing (a) */
Dreg_lo = W [ Ireg -- ] ;
addressing (a) */
Dreg_lo = W [ Preg ] ;
Dreg_lo = W [ Preg ++ Preg ] ;
1
index (a) */
Syntax Terminology
:
Dreg_lo R7–0.L
: , ,
Preg P5–0 SP
:
Ireg I3–0
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length.
Functional Description
The Load Low Data Register Half instruction loads 16 bits from a mem-
ory location indicated by an I-register or a P-register into the least
significant half of a 32-bit data register. The operation does not affect the
most significant half of the data register.
1
See "Indirect and Post-Increment Index Addressing" on page
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* indirect data addressing (a)*/
/* indirect, post-increment data
/* indirect, post-decrement data
/* indirect (a)*/
FP
/* indirect, post-increment
8-29.
Load / Store
8-27