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On-chip Level 2 (L2) Memory
Latency
When cache is enabled, the bus between the core and L2 memory is fully
pipelined for contiguous burst transfers. The cache line fill from on-chip
memory behaves the same for instruction and data fetches. Operations
that miss the cache trigger a cache line replacement. This replacement fills
one 256-bit (32-byte) line with four 64-bit reads. Under this condition,
the L1 cache line fills from the L2 SRAM in
other words, after nine core cycles, the first 64-bit (8-byte) fill is available
for the processor.
latency with cache on.
INSTRUCTION ALIGNMENT UNIT
F
G
E
INSTRUCTION ALIGNMENT UNIT
T+10 A EXECUTES
T+11 B EXECUTES
T+15 F EXECUTES
T+14 E EXECUTES
E
F
G
INSTRUCTION ALIGNMENT UNIT
Figure 6-16. L2 Latency With Cache On
In this example, at the end of 15 core cycles, 32 bytes of instructions or
data have been brought into cache and are available to the sequencer. If all
the instructions contain 16 bits, sixteen instructions are brought into
cache at the end of 15 core cycles. In addition, the first instruction that is
6-44
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Figure 6-16 on page 6-44
A
B
C
D
T+9 ABCD READY
H
B
C
D
A
T+11 EFGH READY
T+13 IJKL READY
TO EXECUTE
T+15 MNOP READY
T+12 C EXECUTES
T+13 D EXECUTES
H
J
K
L
I
CYCLES
9+2+2+2=15
shows an example of L2
A
B
F
E
L2 MEMORY
TO EXECUTE
I
J
M
N
TO EXECUTE
TO EXECUTE
NOTE: AFTER F EXECUTES, GHIJKLMNOP
EXECUTE ON CONSECUTIVE CYCLES.
AFTER P IS IN PIPELINE,
NEW CACHE LINE FILL IS INITIATED.
EACH INSTRUCTION FETCH IS 32 BYTES
64 BITS
64 BITS
T+11
T+9
core cycles. In
C
D
H
G
K
L
O
P
64 BITS
64 BITS
T+13
T+15
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