Hardware Reset - Analog Devices ADSP-BF53x Blackfin Reference

Table 3-6. Resets (Cont'd)
Reset
Core Double-
Fault Reset
Core-Only Soft-
ware Reset

Hardware Reset

The processor chip reset is an asynchronous reset event. The
pin must be deasserted to perform a hardware reset. For more informa-
tion, see the product data sheet.
A hardware-initiated reset results in a system-wide reset that includes both
core and peripherals. After the
ensures that all asynchronous peripherals have recognized and completed a
reset. After the reset, the processor transitions into the Boot mode
sequence configured by the
The pins are dedicated mode control pins. No other functions are
BMODE
shared with these pins, and they may be permanently strapped by tying
them directly to either V
in configure the Boot mode that is employed after hardware reset or
SYSCR
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Source
If the core enters a dou-
ble-fault state, a reset can be
caused by unmasking the
Core Double Fault Reset
Mask bit in the System
Interrupt Controller Inter-
rupt Mask register
(SIC_IMASK).
This reset is caused by exe-
cuting a RAISE1 instruction
or by setting the Software
Reset (SYSRST) bit in the
core Debug Control register
(DBGCTL) via emulation
software through the JTAG
port. The DBGCTL regis-
ter is not visible to the mem-
ory map.
RESET
BMODE
or V
DD
Operating Modes and States
Result
Resets both the core and the peripherals,
excluding the RTC block and most of the
DPMC.
The SWRST register can be read to determine
whether the reset source was Core Double
Fault.
Resets only the core.
The peripherals do not recognize this reset.
pin is deasserted, the processor
state.
. The pins and the corresponding bits
SS
input
RESET
3-13