Analog Devices ADSP-BF53x Blackfin Reference page 275

(
IMEM_CONTROL
respectively. These registers are shown in
Figure 6-9 on page
Each CPLB entry consists of a pair of 32-bit values. For instruction
fetches:
•
ICPLB_ADDR[n]
the CPLB descriptor.
•
ICPLB_DATA[n]
CPLB descriptor.
For data operations:
•
DCPLB_ADDR[m]
the CPLB descriptor.
•
DCPLB_DATA[m]
CPLB descriptor.
There are two default CPLB descriptors for data accesses to the scratchpad
data memory and to the system and core MMR space. These default
descriptors define the above space as non-cacheable, so that additional
CPLBs do not need to be set up for these regions of memory.
If valid CPLBs are set up for this space, the default CPLBs are
ignored.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
) and L1 Data Memory Control (
6-25, respectively.
defines the start address of the page described by
defines the properties of the page described by the
defines the start address of the page described by
defines the properties of the page described by the
DMEM_CONTROL
Figure 6-2 on page 6-7
Memory
) registers,
and
6-47