Analog Devices ADSP-BF53x Blackfin Reference page 862

Arithmetic Operations Instructions
Table C-17. Arithmetic Operations Instructions (Sheet 8 of 44)
Instruction
and Version
Modify, Increment
Ireg += Mreg (brev)
Modify, Increment
Dreg = (A0 += A1)
Modify, Increment
Dreg_lo = (A0 += A1)
Modify, Increment
NOTE: When issuing compatible load/store instructions in parallel with a Multiply 16-Bit Operands
instruction, add 0x0800 0000 to the Multiply 16-Bit Operands opcode.
Dreg_hi = (A0 += A1)
Multiply 16-Bit Operands
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi
Multiply 16-Bit Operands
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi (FU)
Multiply 16-Bit Operands
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi (IS)
C-62 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x9EE0— 1 0 0 1 1 1 1 0 1 1 1 0 Mreg
0x9EEF
0xC40B 003F— 1 1 0 0 0 1 0 x x x 0 0 1 0 1 1
0xC40B 0E00
0 0 0 0 Dest
0xC40B 403F— 1 1 0 0 0 1 0 x x x 0 0 1 0 1 1
0xC40B 4E00
0 1 0 0 Dest
0xC42B 403F— 1 1 0 0 0 1 0 x x x 1 0 1 0 1 1
0xC42B 4E00
0 1 0 0 Dest
0xC200 2000— 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0xC200 27FF
0 0 1 0 0 Dreg
0xC280 2000— 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0
0xC280 27FF
0 0 1 0 0 Dreg
C300 2000— 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0
0xC300 27FF
0 0 1 0 0 Dreg
Bin
0 0 0 1 1 1 1 1 1
Dreg #
0 0 0 1 1 1 1 1 1
Dreg #
0 0 0 1 1 1 1 1 1
Dreg #
Dest. src_reg_
half Dreg # 0 Dreg #
Dest. src_reg_
half Dreg # 0 Dreg #
Dest. src_reg_
half Dreg # 0 Dreg #
Ireg #
#
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #