Analog Devices ADSP-BF53x Blackfin Reference page 947

Table C-22. 16-Bit Opcode Instructions (Sheet 8 of 14)
Instruction
and Version
Bit Set
BITSET (Dreg, uimm5)
Bit Toggle
BITTGL (Dreg, uimm5)
Bit Clear
BITCLR (Dreg, uimm5)
Arithmetic Shift
Dreg >>>= uimm5
Logical Shift
Dreg >>= uimm5
Logical Shift
Dreg <<= uimm5
Add
Dreg = Dreg + Dreg
Subtract
Dreg = Dreg – Dreg
AND
Dreg = Dreg & Dreg
OR
Dreg = Dreg | Dreg
Exclusive-OR
Dreg = Dreg ^ Dreg
Add
Preg = Preg + Preg
Logical Shift
Preg = Preg << 1
NOTE: The special case of the Preg = Preg + Preg Add instruction, where both input operands are the
same Preg (e.g., p3 = p0+p0;), produces the same opcode as the Logical Shift instruction Preg = Preg << 1
that accomplishes the same function. Both syntaxes double the input operand value, then place the result
in a Preg.
Shift with Add
Preg = Preg + (Preg <<1)
Shift with Add
Preg = Preg + (Preg <<2)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Instruction Opcodes
Opcode
Range
0x4A00—
0x4AFF
0x4B00—
0x4BFF
0x4C00—
0x4CFF
0x4D00—
0x4DFF
0x4E00—
0x4EFF
0x4F00—
0x4FFF
0x5000—
0x51FF
0x5200—
0x53FF
0x5400—
0x55FF
0x5600—
0x57FF
0x5800—
0x59FF
0x5A00—
0x5BFF
0x5A00—
0x5BFF
0x5C00—
0x5DFF
0x5E00—
0x5FFF
C-147