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ITEST_DATA0 Register
The Instruction Test Data 0 register (
bits of the 64-bit data to be written to or read from by the access. The
register is also used to access tag arrays. This register also
ITEST_DATA0
contains the Valid and Dirty bits, which indicate the state of the cache
line.
Instruction Test Data 0 Register (ITEST_DATA0)
Used to access L1 cache data arrays and tag arrays. When accessing a data array, stores the lower 32 bits of
64-bit words of instruction data to be written to or read from by the access. See
0xFFE0 1400
Used to access the L1 cache tag arrays. The address tag consists of the upper 18 bits and bits 11 and 10 of the
physical address. See
Tag[3:2]
Physical address
Tag[1:0]
Physical address
Figure 6-8. Instruction Test Data 0 Register
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X
X
X
X
X
X
X
X
15 14 13 12 11 10 9
8
X
X
X
X
X
X
X
X
"Cache Lines" on page
6-10.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X
X
X
X
X
X
X
X
15 14 13 12 11 10
9
8
X
X
X
X
X
X
X
X
) stores the lower 32
ITEST_DATA0
"Cache Lines" on page
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
Memory
6-10.
Reset = Undefined
Data[31:16]
Data[15:0]
Reset = Undefined
Tag[19:4]
Physical address
Valid
0 - Cache line is not valid
1 - Cache line contains valid
data
LRUPRIO
0 - LRUPRIO is cleared for
this entry
1 - LRUPRIO is set for this
entry. See
"ICPLB_DATAx
Registers" on page 6-55
and
"IMEM_CONTROL Register"
on page
6-5.
6-23
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