Analog Devices ADSP-BF53x Blackfin Reference page 365

:
Mreg M3–0
: 6-bit unsigned field that must be a multiple of 4, with a range of
uimm6m4
0 through 60 bytes
: 7-bit unsigned field that must be a multiple of 4, with a range of
uimm7m4
4 through 128 bytes
: 17-bit unsigned field that must be a multiple of 4, with a range
uimm17m4
of 0 through 131,068 bytes (0x0000 through 0xFFFC)
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length. Comment
(b) identifies 32-bit instruction length.
Functional Description
The Store Data Register instruction stores the contents of a 32-bit D-reg-
ister to a 32-bit memory location. The destination Pointer register can be
a P-register, I-register, or the Frame Pointer.
The indirect address and offset must yield an even multiple of 4 to main-
tain 4-byte word address alignment. Failure to maintain proper alignment
causes a misaligned memory access exception.
The instruction versions that explicitly modify
optional circular buffering. See
on page 1-21
disable it prior to issuing this instruction by clearing the Length
Register (
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
for more details. Unless circular buffering is desired,
) corresponding to the
Lreg
Ireg
"Automatic Circular Addressing"
used in this instruction.
Ireg
Load / Store
support
8-41