Instruction Overview
Required Mode
User & Supervisor
Parallel Issue
The Index Register versions of this instruction can be issued in parallel
with specific other instructions. For details, see
tions" on page
The Data Register and Pointer Register versions of this instruction cannot
be issued in parallel with other instructions.
Example
r0 += 40 ;
p5 += -4 ;
i0 += 2 ;
i1 += 4 ;
Also See
Subtract Immediate
Special Applications
None
15-18
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
20-1.
/* decrement by adding a negative value */
"Issuing Parallel Instruc-