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Note the System Interrupt to Core Event mappings shown are the default
values at reset and can be changed by software.
System Interrupt Processing
Referring to
Figure 4-4 on page
A) is generated by an interrupt-enabled peripheral:
1.
SIC_ISR
are asserted but not yet serviced (that is, an interrupt service rou-
tine hasn't yet cleared the interrupt).
2.
SIC_IWR
state based on this interrupt request.
3.
SIC_IMASK
system level. If Interrupt A is not masked, the request proceeds to
Step 4.
4. The
SIC_IARx
smaller set of general-purpose core interrupts (
determine the core priority of Interrupt A.
5.
adds Interrupt A to its log of interrupts latched by the core
ILAT
but not yet actively being serviced.
6.
masks off or enables events of different core priorities. If the
IMASK
event corresponding to Interrupt A is not masked, the process
IVGx
proceeds to Step 7.
7. The Event Vector Table (EVT) is accessed to look up the appropri-
ate vector for Interrupt A's interrupt service routine (ISR).
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
4-33, note when an interrupt (Interrupt
logs the request and keeps track of system interrupts that
checks to see if it should wake up the core from an idled
masks off or enables interrupts from peripherals at the
registers, which map the peripheral interrupts to a
Program Sequencer
),
IVG7 – IVG15
4-31
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