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Table C-23. 32-Bit Opcode Instructions (Sheet 24 of 40)
Instruction
and Version
Subtract
Dreg_lo = Dreg_hi – Dreg_lo (S)
Subtract
Dreg_lo = Dreg_hi – Dreg_hi (NS)
Subtract
Dreg_lo = Dreg_hi – Dreg_hi (S)
Add
Dreg = Dreg + Dreg (NS)
Add
Dreg = Dreg + Dreg (S)
Subtract
Dreg = Dreg – Dreg (NS)
Subtract
Dreg = Dreg – Dreg (S)
Vector Add / Subtract
Dreg = Dreg + Dreg, Dreg = Dreg – Dreg
Vector Add / Subtract
Dreg = Dreg + Dreg, Dreg = Dreg – Dreg (S)
Add/Subtract-Prescale Up
Dreg_lo = Dreg + Dreg (RND12)
Add/Subtract-Prescale Up
Dreg_lo = Dreg – Dreg (RND12)
Add/Subtract-Prescale Down
Dreg_lo = Dreg + Dreg (RND20)
Add/Subtract-Prescale Down
Dreg_lo = Dreg – Dreg (RND20)
Vector Maximum
Dreg = MAX (Dreg, Dreg) (V)
Vector Minimum
Dreg = MIN (Dreg, Dreg) (V)
Vector Absolute Value
Dreg = ABS Dreg (V)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Instruction Opcodes
Opcode
Range
0xC403 A000—
0xC403 AE3F
0xC403 C000—
0xC403 CE3F
0xC403 E000—
0xC403 EE3F
0xC404 0000—
0xC404 0E3F
0xC404 2000—
0xC404 2E3F
0xC404 4000—
0xC404 4E3F
0xC404 6000—
0xC404 6E3F
0xC404 8000—
0xC404 8FFF
0xC404 A000—
0xC404 AFFF
0xC405 0000—
0xC405 0E3F
0xC405 4000—
0xC405 4E3F
0xC405 9000—
0xC405 9E3F
0xC405 D000—
0xC405 DE3F
0xC406 0000—
0xC406 0E3F
0xC406 4000—
0xC406 4E3F
0xC406 8000—
0xC406 8E38
C-177
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