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Instructions Listed By Operation Code
Table C-23. 32-Bit Opcode Instructions (Sheet 39 of 40)
Instruction
and Version
Load Data Register
Dreg = [ Preg + uimm17m4 ]
Load Data Register
Dreg = [ Preg – uimm17m4 ]
Load Half Word, Zero Extended
Dreg = W [ Preg + uimm16m2 ] (Z)
Load Half Word, Zero Extended
Dreg = W [ Preg – uimm16m2 ] (Z)
Load Byte, Zero Extended
Dreg = B [ Preg + uimm15 ] (Z)
Load Byte, Zero Extended
Dreg = B [ Preg – uimm15] (Z)
Load Pointer Register
Preg = [ Preg + uimm17m4 ]
Load Pointer Register
Preg = [ Preg – uimm17m4 ]
Load Half Word, Sign Extended
Dreg = W [ Preg + uimm16m2 ] (X)
Load Half Word, Sign Extended
Dreg = W [ Preg – uimm16m2 ] (X)
Load Byte, Sign Extended
Dreg = B [ Preg + uimm15 ] (X)
Load Byte, Sign Extended
Dreg = B [ Preg – uimm15] (X)
Store Data Register
[ Preg + uimm17m4 ] = Dreg
Store Data Register
[ Preg – uimm17m4 ] = Dreg
Store Low Data Register Half
W [ Preg + uimm16m2 ] = Dreg
Store Low Data Register Half
W [ Preg – uimm16m2 ] = Dreg
C-192
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range
0xE400 0000—
0xE4EF 7FFF
0xE400 8000—
0xE43F FFFF
0xE440 0000—
0xE47F 8FFF
0xE440 8000—
0xE47F FFFF
0xE480 0000—
0xE4BF 7FFF
0xE480 8000—
0xE4BF FFFF
0xE500 0000—
0xE53F 7FFF
0xE500 8000—
0xE53F FFFF
0xE540 0000—
0xE57F 8FFF
0xE540 8000—
0xE57F FFFF
0xE580 0000—
0xE5BF 7FFF
0xE580 8000—
0xE5BF FFFF
0xE600 0000—
0xE63F 7FFF
0xE600 8000—
0xE63F FFFF
0xE640 0000—
0xE67F 7FFF
0xE640 8000—
0xE67F FFFF
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