Glossary; Register Names - Analog Devices ADSP-BF53x Blackfin Reference

Glossary

The following terms appear throughout this document. Without trying to
explain the Blackfin processor, here are the terms used with their defini-
tions. See the Blackfin Processor Hardware Reference for your specific
product for more details on the architecture.

Register Names

The architecture includes the registers shown in
Table 1-1. Registers
Register Description
Accumulators The set of 40-bit registers A1 and A0 that normally contain data that is being
manipulated. Each Accumulator can be accessed in five ways: as one 40-bit regis-
ter, as one 32-bit register (designated as A1.W or A0.W), as two 16-bit registers
similar to Data Registers (designated as A1.H, A1.L, A0.H, or A0.L) and as one
8-bit register (designated A1.X or A0.X) for the bits that extend beyond bit 31.
Data The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6, and R7) that normally
Registers contain data for manipulation. Abbreviated D-register or Dreg. Data Registers
can be accessed as 32-bit registers, or optionally as two independent 16-bit regis-
ters. The least significant 16 bits of each register is called the "low" half and is
designated with ".L" following the register name. The most significant 16 bit is
called the "high" half and is designated with ".H" following the name. Example:
R7.L, r2.h, r4.L, R0.h.
Pointer The set of 32-bit registers (P0, P1, P2, P3, P4, P5, including SP and FP) that
Registers normally contain byte addresses of data structures. Accessed only as a 32-bit reg-
ister. Abbreviated P-register or Preg. Example: p2, p5, fp, sp.
Stack Pointer SP; contains the 32-bit address of the last occupied byte location in the stack.
The stack grows by decrementing the Stack Pointer. A subset of the Pointer Reg-
isters.
Frame Pointer FP; contains the 32-bit address of the previous Frame Pointer in the stack,
located at the top of a frame. A subset of the Pointer Registers.
Loop Top LT0 and LT1; contains 32-bit address of the top of a zero overhead loop.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Introduction
Table 1-1.
1-13