Analog Devices ADSP-BF53x Blackfin Reference page 1018

Index
instruction address, 4-3
instruction-address-range watchpoints,
21-2
instruction address (WPIA[14:0]) field,
21-6
instruction address (WPIA[30:15]) field,
21-6
instruction alignment unit,
instruction cache
coherency, 6-16
invalidating, 17-1
invalidation, 6-18
L1 memory, 6-2
management, 6-16
instruction cache flush (IFLUSH)
instruction, 6-6, 6-18, 17-9,
instruction CPLB enable (ENICPLB) bit,
6-7, 6-51
instruction decode (DEC),
instruction fetch, 4-8, 6-47
time loop, 4-24
instruction fetch 1 (IFin1),
instruction fetch 2 (IF2),
instruction fetch 3 (IF3),
instruction loop buffer,
instruction memory control
(IMEM_CONTROL) register, 6-5,
6-47
instruction memory unit,
instruction opcodes
abort, C-100
add, C-55
add immediate, C-59
add on sign, C-107
add/subtract - prescale down,
add/subtract - prescale up,
add with shift, C-46
AND, C-43
arithmetic shift, C-46
bit clear, C-44
I-16 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
4-8
C-101
4-7
4-7
4-7
4-7
4-24
4-8
C-58
C-59
instruction opcodes
bit field deposit, C-44
bit field extraction, C-44
bit multiplex, C-45
bit set, C-44
bit test, C-44
bit toggle, C-44
bit-wise exclusive-OR,
byte align, C-102
CALL, C-13
compare accumulator,
compare data register,
compare pointer, C-40
compare-select (VIT_MAX),
core synchronize, C-99
data cache flush, C-101
data cache line invalidate,
data cache prefetch,
disable alignment exception for load,
C-102
disable interrupts, C-99
divide primitive, C-60
dual 16-bit accumulator extraction with
addition, C-103
dual 16-bit add / clip,
enable interrupts, C-99
exclusive-OR, C-43
exponent detection,
force emulation, C-99
force exception, C-99
force interrupt / reset,
idle, C-99
instruction cache flush,
JUMP, C-13
linkage, C-38
load byte – sign-extended,
load byte – zero-extended,
load data register, C-17
load half-word – sign-extended,
load half-word – zero-extended,
(continued)
C-43
C-41
C-39
C-107
C-101
C-101
C-102
C-60
C-99
C-101
C-22
C-22
C-20
C-19