Analog Devices ADSP-BF53x Blackfin Reference page 231

CORE CLOCK
(CCLK) DOMAIN
SYSTEM CLOCK
(SCLK) DOMAIN
PERIPHERAL
ACCESS
BUS (PAB)
NON-DMA PERIPHERALS
Figure 6-1. Processor Memory Architecture
The L1 memory provides:
• A modified Harvard architecture, allowing up to four core memory
accesses per clock cycle (one 64-bit instruction fetch, two 32-bit
data loads, and one pipelined 32-bit data store)
• Simultaneous system DMA, cache maintenance, and core accesses
• SRAM access at processor clock rate (
rithms and fast context switching
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
64
CORE
32
PROCESSOR
32
32
CONTROLLER
16
DMA PERIPHERALS
16
DMA ACCESS BUS
(DAB)
L1 MEMORY
INSTRUCTION
LOAD DATA
LOAD DATA
STORE DATA
DMA
16
CORE
BUS (DCB)
DMA
DMA
16
EXTERNAL
BUS (DEB)
EBIU
16
16
) for critical DSP algo-
CCLK
Memory
16
EXTERNAL
ACCESS
BUS (EAB)
EXTERNAL
PORT
BUS (EPB)
6-3