Table of Contents
Advertisement
"Exceptions" on page 4-47
part of the operating system (OS) kernel that implements the CPLB
replacement policy.
Before CPLBs are enabled, valid CPLB descriptors must be in place
for both the Page Descriptor Table and the MMU exception han-
dler. The
they are not inadvertently replaced in software.
The handler uses the faulting address to index into the Page Descriptor
Table structure to find the correct CPLB descriptor data to load into one
of the on-chip CPLB register pairs. If all on-chip registers contain valid
CPLB entries, the handler selects one of the descriptors to be replaced,
and the new descriptor information is loaded. Before loading new descrip-
tor data into any CPLBs, the corresponding group of sixteen CPLBs must
be disabled using:
• The Enable DCPLB (
data descriptors, or
• The Enable ICPLB (
instruction descriptors
The CPLB replacement policy and algorithm to be used are the responsi-
bility of the system MMU exception handler. This policy, which is
dictated by the characteristics of the operating system, usually implements
a modified LRU (Least Recently Used) policy, a round robin scheduling
method, or pseudo random replacement.
After the new CPLB descriptor is loaded, the exception handler returns,
and the faulting memory operation is restarted. this operation should now
find a valid CPLB descriptor for the requested address, and it should pro-
ceed normally.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
for more information). The handler is typically
bits of these CPLB descriptors are commonly set so
LOCK
ENDCPLB
ENICPLB
) bit in the
DMEM_CONTROL
) bit in the
IMEM_CONTROL
Memory
register for
register for
6-51
Advertisement
Table of Contents
