Analog Devices ADSP-BF53x Blackfin Reference page 1008

Index
cache line
components, 6-10
definition, 6-74
replacement unit, 6-15
states, 6-34
cache memory, programming model,
cache misses
cache controller, 6-33
contrasted with cache hits,
definition, 6-74
replacement policy, 6-15
cache way lock (ILOC[3:0]) field, 6-5, 6-7,
6-17
CALL instruction
direct, 4-12
dynamic range, 4-12
indirect, 4-12
opcode range, C-13
range, 4-12
return address, 4-10
subroutines, 4-13
syntax, 7-8
carry bits, 2-14
CC (control code) bit,
diagram, 2-25
JUMP instruction, 4-10
ways of accessing, 4-18
CCEN (cycle counter enable) bit,
CEC (core event controller), 1-7, 4-48,
4-55
choice of one register within a group,
notation convention,
circular addressing, 1-21
automatic, 1-21
behavior, 1-21
buffer register initialization, 15-17,
15-35, 15-39, 15-91
buffer registers, 1-21
buffer registers listed,
disabling, 1-14, 1-21, 1-22,
I-6 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
6-2
6-13
1-15
21-26
C-5
1-21
C-3
circular addressing
enabling, 1-22
example instructions,
initializing buffer registers, 8-11, 8-24,
8-28, 8-42, 8-46,
load data register, 8-11
load high data register half,
load low data register half,
store data register, 8-41
store high data register half,
store low data register half,
supporting add immediate instructions,
15-16
supporting modify – decrement
instructions, 15-35
supporting modify – increment
instructions, 15-39
supporting subtract immediate
instructions, 15-90
circular buffer addressing
defined, 5-12
registers, 5-12
wraparound, 5-15
circular buffers, 5-8
addressing, 5-12
contents, 1-21
maximum length of,
setting addresses for,
circular data buffers (figure),
clean, memory term definition,
CLI (disable interrupts) instruction, 6-74,
16-13
CMPLP[1:0] field, 21-17
code examples
core MMR programming,
epilog code for nested ISR,
exception handler, 4-68
exception routine, 4-70
interrupt enabling and disabling,
load base of MMRs,
(continued)
1-22
8-50
8-24
8-28
8-46
8-50
1-21
5-3
5-14
6-75
6-74
4-54
6-74
6-74