Analog Devices ADSP-BF53x Blackfin Reference page 1034

Index
shifter
instructions listed, 2-53
operations, 2-48
register shifts, defined,
register shifts, example,
status flags, 2-53
tasks performed, 1-3
three-operand shifts,
two-operand shifts, defined,
shift instructions
arithmetic shift, 2-48, 14-7,
ASHIFT, 2-48
logical shift, 2-48, 14-14,
LSHIFT, 2-48
ROT, 2-48
rotate, 2-48
shift with add, 14-5,
vector arithmetic shift, 19-23,
vector logical shift, 19-28,
shift / rotate operations instructions,
short jump (JUMP.S) instruction,
SIC_IARx (system interrupt assignment)
register, 4-31
SIC_IARx (system interrupt assignment)
register 0, 4-37
SIC_IARx (system interrupt assignment)
registers
SIC_IMASK (system interrupt controller
interrupt mask) register, 3-13,
SIC_ISR (system interrupt status) register,
4-31
SIC_IWR (system interrupt wakeup
enable) register, 4-31
SIC (system interrupt controller), 1-7, 1-8,
4-35, 4-55
SIGN (add on) instruction,
sign bit (SIGNBITS) instruction. See
SIGNBITS
SIGNBITS (sign bit) instruction, 15-83,
C-95
I-32 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
(continued)
2-50
2-50
2-50
2-49
C-46
C-50
C-46
C-114
C-115
C-46
4-11
4-31
19-3
signed fraction operands (T)
multiply 16-bit operands instruction,
15-43
multiply and multiply-accumulate to
half-register instruction,
use with multiply instructions, 15-43,
15-58
signed numbers
data format, 2-4
ranges, D-4
supported by Blackfin,
two's-complement, 2-5
signed operator (IS)
multiply 16-bit operands instruction,
15-43
multiply and multiply-accumulate to
accumulator instruction,
multiply and multiply-accumulate to
data register instruction,
multiply and multiply-accumulate to
half-register instruction,
use with multiply instructions, 15-43,
15-53, 15-58, 15-67
sign extended (X) flag, use with bit field
instructions, 13-10,
sign extending data, 2-12
SIGN instruction, C-107
SIMD video ALU operations,
single 16-bit operations, defined with
example, 2-27
single 32-bit operations, defined with
example, 2-29
single step exception, 4-66
small loop count values,
SNEN (self-nesting interrupt enable) bit,
21-26
software interrupt handlers,
software loops, zero-overhead,
15-58
D-1
15-53
15-67
15-58
13-16
2-35
7-16
4-30
7-15