Analog Devices ADSP-BF53x Blackfin Reference page 954

Instructions Listed By Operation Code
32-Bit Opcode Instructions
Table C-23 lists the instructions that are represented by 32-bit opcodes.
Table C-23. 32-Bit Opcode Instructions (Sheet 1 of 40)
Instruction
and Version
Vector Multiply and Multiply-Accumulate
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi
Multiply and Multiply-Accumulate to Accumulator
A1 = Dreg_lo_hi * Dreg_lo_hi
Vector Multiply and Multiply-Accumulate
Dreg_lo = (A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi) ,
A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi
Multiply and Multiply-Accumulate to Accumulator
A1 += Dreg_lo_hi * Dreg_lo_hi
Multiply and Multiply-Accumulate to Accumulator
A1 –= Dreg_lo_hi * Dreg_lo_hi
Multiply and Multiply-Accumulate to Accumulator
A0 = Dreg_lo_hi * Dreg_lo_hi
Multiply and Multiply-Accumulate to Accumulator
A0 += Dreg_lo_hi * Dreg_lo_hi
Multiply and Multiply-Accumulate to Accumulator
A0 –= Dreg_lo_hi * Dreg_lo_hi
No Op
MNOP
Multiply and Multiply-Accumulate to Half Register
Dreg_lo = (A0 = Dreg_lo_hi * Dreg_lo_hi)
Multiply and Multiply-Accumulate to Half Register
Dreg_lo = (A0 += Dreg_lo_hi * Dreg_lo_hi)
Multiply and Multiply-Accumulate to Half Register
Dreg_lo = (A0 –= Dreg_lo_hi * Dreg_lo_hi)
Move Register Half
Dreg_lo = A0
C-154 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range
0xC000 0000—
0xC003 DE3F
0xC000 1800—
0xC000 D83F
0xC000 2000—
0xC003 FFFF
0xC001 1800—
0xC001 D83F
0xC002 1800—
0xC002 D83F
0xC003 0000—
0xC003 063F
0xC003 0800—
0xC003 0E3F
0xC003 1000—
0xC003 163F
0xC003 1800
0xC003 2000—
0xC003 27FF
0xC003 2800—
0xC003 0FFF
0xC003 3000—
0xC003 37FF
0xC003 3800—
0xC003 39C0