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Instruction Test Registers
ITEST_DATA1 Register
Instruction Test Data registers (
cache data arrays. They contain either the 64-bit data that the access is to
write to or the 64-bit data that the access is to read from. The Instruction
Test Data 1 register (
Instruction Test Data 1 Register (ITEST_DATA1)
Used to access L1 cache data arrays and tag arrays. When accessing a data array, stores
the upper 32 bits of 64-bit words of instruction data to be written to or read from by the
access. See
"Cache Lines" on page
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0xFFE0 1404
15 14 13 12 11 10 9
When accessing tag arrays, all bits are reserved.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9
Figure 6-7. Instruction Test Data 1 Register
6-22
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
ITEST_DATA[1:0]
ITEST_DATA1
6-10.
X
X
X
X
X
X
X
X
8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8
X
X
X
X
X
X
X
X
) are used to access L1
) stores the upper 32 bits.
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Reset = Undefined
X
Data[63:48]
X
Data[47:32]
Reset = Undefined
X
X
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