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Options
The Store Byte instruction supports the following options.
• Post-increment the destination pointer by 1 byte to maintain byte
alignment.
• Post-decrement the destination pointer by 1 byte to maintain byte
alignment.
• Offset the destination pointer with a 16-bit signed constant.
Flags Affected
None
Required Mode
User & Supervisor
Parallel Issue
The 16-bit versions of this instruction can be issued in parallel with spe-
cific other instructions.
Instructions" on page 20-1.
The 32-bit versions of this instruction cannot be issued in parallel with
other instructions.
Example
b [ p0 ] = r3 ;
b [ p1 ++ ] = r7 ;
b [ sp -- ] = r2 ;
b [ p4 + 0x100F ] = r0 ;
b [ p4 - 0x53F ] = r0 ;
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
For more information, see "Issuing Parallel
Load / Store
8-55
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