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Table C-1. Registers (Cont'd)
Register
Index Register
Modify Registers
Length Registers
Base Registers
Functional Units
The architecture includes three processor sections.
Table C-2. Processor Sections
Processor
Data Address Generator
(DAG)
Multiply and Accumulate
Unit (MAC)
Arithmetic Logical Unit
(ALU)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Description
The set of 32-bit registers I0, I1, I2, I3 that normally contain byte addresses of
data structures. Abbreviated I-register or Ireg.
The set of 32-bit registers M0, M1, M2, M3 that normally contain offset val-
ues that are added or subtracted to one of the Index registers. Abbreviated as
Mreg.
The set of 32-bit registers L0, L1, L2, L3 that normally contain the length (in
bytes) of the circular buffer. Abbreviated as Lreg. Clear Lreg to disable circular
addressing for the corresponding Ireg. Example: Clear L3 to disable circular
addressing for I3.
The set of 32-bit registers B0, B1, B2, B3 that normally contain the base
address (in bytes) of the circular buffer. Abbreviated as Breg.
Description
Calculates the effective address for indirect and indexed memory
accesses. Operates on the Pointer, Index, Modify, Length, and Base
Registers. Consists of two units—DAG0 and DAG1.
Performs multiply computations and accumulations on data. Operates
on the Data Registers and Accumulators. Consists of two units
(MAC0 and MAC1), each associated with an Accumulator (A0 and
A1, respectively). Each MAC operates in conjunction with an Arith-
metic Logical Unit.
Performs arithmetic computations and binary shifts on data. Operates
on the Data Registers and Accumulators. Consists of two units (ALU0
and ALU1), each associated with an Accumulator (A0 and A1, respec-
tively). Each ALU operates in conjunction with a Multiply and Accu-
mulate Unit.
Instruction Opcodes
C-3
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