Analog Devices ADSP-BF53x Blackfin Reference page 902

Video Pixel Operations Instructions
Video Pixel Operations Instructions
Table C-20. Video Pixel Operations Instructions (Sheet 1 of 5)
Instruction
and Version
Byte Align
Dreg = ALIGN8 (Dreg, Dreg)
Byte Align
Dreg = ALIGN16 (Dreg, Dreg)
Byte Align
Dreg = ALIGN24 (Dreg, Dreg)
Disable Alignment Exception for
Load
NOTE: When issuing compatible load/store instructions in parallel with a Disable Alignment Exception
for Load instruction, add 0x0800 0000 to the Disable Alignment Exception for Load opcode.
DISALGNEXCPT
Dual 16-Bit Add / Clip
Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (LO)
Dual 16-Bit Add / Clip
Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (HI)
C-102 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC60D 0000— 1 1 0 0 0 1 1 0 0 x x 0 1 1 0 1
0xC60D 0E3F
0 0 0 0 Dest.
0xC60D 4000— 1 1 0 0 0 1 1 0 0 x x 0 1 1 0 1
0xC60D 4E3F
0 1 0 0 Dest.
0xC60D 800— 1 1 0 0 0 1 1 0 0 x x 0 1 1 0 1
0xC60D 8E3F0
1 0 0 0 Dest.
0xC412 C000 1 1 0 0 0 1 0 x x x 0 1 0 0 1 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xC417 0000— 1 1 0 0 0 1 0 x x x 0 1 0 1 1 1
0xC417 0E3F
0 0 0 0 Dest. 0
0xC437 0000— 1 1 0 0 0 1 0 x x x 1 1 0 1 1 1
0xC437 0E3F
0 0 0 0 Dest. 0
Bin
x x x Source 0
Dreg # Dreg #
x x x Source 0
Dreg # Dreg #
x x x Source 0
Dreg # Dreg #
0 0 0 Source 0
Dreg # Dreg #
0 0 0 Source 0
Dreg # Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #