Examples - Analog Devices ADSP-BF53x Blackfin Reference

Examples

Table 20-4. Group2 Compatible 16-Bit Instructions
Instruction Name
Load / Store
Load Data Register
Load High Data Register Half
Load Low Data Register Half
Store Data Register
Store High Data Register Half
Store Low Data Register Half
External Event Management
No Op
Examples
Two Parallel Memory Access Instructions
/* Subtract-Absolute-Accumulate issued in parallel with the mem-
ory access instructions that fetch the data for the next SAA
instruction. This sequence is executed in a loop to flip-flop
back and forth between the data in R1 and R3, then the data in R0
and R2. */
saa (r1:0, r3:2) || r0=[i0++] || r2=[i1++] ;
saa (r1:0, r3:2)(r) || r1=[i0++] || r3=[i1++] ;
mnop || r1 = [i0++] || r3 = [i1++] ;
20-8 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Notes
Ireg versions only.
Ireg versions only.
Ireg versions only.
Ireg versions only.
Ireg versions only.
Ireg versions only.
16-bit NOP only.