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Table C-17. Arithmetic Operations Instructions (Sheet 17 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate
to Accumulator
NOTE: When issuing compatible load/store instructions in parallel with a Multiply and Multiply-Accumu-
late instruction, add 0x0800 0000 to the Multiply and Multiply-Accumulate opcode.
A0 – = Dreg_lo_hi * Dreg_lo_hi (W32)
Multiply and Multiply-Accumulate
to Accumulator
A1 = Dreg_lo_hi * Dreg_lo_hi
Multiply and Multiply-Accumulate
to Accumulator
A1 = Dreg_lo_hi * Dreg_lo_hi (FU)
Multiply and Multiply-Accumulate
to Accumulator
A1 = Dreg_lo_hi * Dreg_lo_hi (IS)
Multiply and Multiply-Accumulate
to Accumulator
A1 = Dreg_lo_hi * Dreg_lo_hi (W32)
Multiply and Multiply-Accumulate
to Accumulator
A1 = Dreg_lo_hi * Dreg_lo_hi (M)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC063 1000—
1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1
0xC063 163F
0 0 0 1 0 Dreg
0xC000 1800—
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xC000 D83F
Dreg
half
0xC080 1800—
1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0xC080 D83F
Dreg
half
0xC100 1800—
1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0
0xC100 D83F
Dreg
half
0xC060 1800—
1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0
0xC060 D83F
Dreg
half
0xC010 1800—
1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0xC010 D83F
Dreg
half
Instruction Opcodes
Bin
0 0 0 src_reg_
half
0 1 1 0 0 0 0 0 src_reg_
0 1 1 0 0 0 0 0 src_reg_
0 1 1 0 0 0 0 0 src_reg_
0 1 1 0 0 0 0 0 src_reg_
0 1 1 0 0 0 0 0 src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
0 Dreg #
1 Dreg #
src_reg_
0 Dreg #
1 Dreg #
src_reg_
0 Dreg #
1 Dreg #
src_reg_
0 Dreg #
1 Dreg #
src_reg_
0 Dreg #
1 Dreg #
C-71
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