Analog Devices ADSP-BF53x Blackfin Reference page 951

Table C-22. 16-Bit Opcode Instructions (Sheet 12 of 14)
Instruction
and Version
Load High Data Register Half
Dreg_hi = W [ Ireg ++ ]
Load Data Register
Dreg = [ Ireg – – ]
Load Low Data Register Half
Dreg_lo = W [ Ireg – – ]
Load High Data Register Half
Dreg_hi = W [ Ireg – – ]
Load Data Register
Dreg = [ Ireg ]
Load Low Data Register Half
Dreg_lo = W [ Ireg ]
Load High Data Register Half
Dreg_hi = W [ Ireg ]
Load Data Register
Dreg = [ Ireg ++ Mreg ]
Store Data Register
[ Ireg ++ ] = Dreg
Store Low Data Register Half
W [ Ireg ++ ] = Dreg_lo
Store High Data Register Half
W [ Ireg ++ ] = Dreg_hi
Modify-Increment
Ireg += Mreg
Modify-Decrement
Ireg –= Mreg
Store Data Register
[ Ireg – – ] = Dreg
Store Low Data Register Half
W [ Ireg – – ] = Dreg_lo
Store High Data Register Half
W [ Ireg – – ] = Dreg_hi
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Instruction Opcodes
Opcode
Range
0x9C40—
0x9C5F
0x9C80—
0x9C9F
0x9CA0—
0x9CBF
0x9CC0—
0x9CDF
0x9D00—
0x9D1F
0x9D20—
0x9D3F
0x9D40—
0x9D5F
0x9D80—
0x9DFF
0x9E00—
0x9E1F
0x9E20—
0x9E3F
0x9E40—
0x9E5F
0x9E60—
0x9E6F
0x9E70—
0x9E7F
0x9E80—
0x9E9F
0x9EA0—
0x9EBF
0x9EC0—
0x9EDF
C-151