Table of Contents
Advertisement
unsigned, a mixture, or a rounding operation). The 32-bit result from the
multipliers is assumed to be signed; it is sign-extended across the full
40-bit width of the
The processor supports two modes of format adjustment: the fractional
mode for fractional operands (1.15 format with 1 sign bit and 15 frac-
tional bits) and the integer mode for integer operands (16.0 format).
When the processor multiplies two 1.15 operands, the result is a 2.30
(2 sign bits and 30 fractional bits) number. In the fractional mode, the
multiplier automatically shifts the multiplier product left one bit before
transferring the result to the multiplier result register (
the redundant sign bit causes the multiplier result to be in 1.31 format,
which can be rounded to 1.15 format. The resulting format appears in
Figure 2-5 on page
In the integer mode, the left shift does not occur. For example, if the oper-
ands are in the 16.0 format, the 32-bit multiplier result would be in 32.0
format. A left shift is not needed and would change the numerical
representation. This result format appears in
Multiplier results generate status information when they update accumu-
lators or when they are transferred to a destination register in the register
file. For more information, see
2-38.
Shifter Data Types
Many operations in the shifter are explicitly geared to signed (two's-com-
plement) or unsigned values—logical shifts assume unsigned magnitude
or binary string values, and arithmetic shifts assume two's-complement
values.
The exponent logic assumes two's-complement numbers. The exponent
logic supports block floating point, which is also based on two's-comple-
ment fractions.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
or
registers.
A0
A1
2-18.
"Multiplier Instruction Summary" on page
Computational Units
,
). This shift of
A0
A1
Figure 2-6 on page
2-19.
2-15
Advertisement
Table of Contents
