Analog Devices ADSP-BF53x Blackfin Reference page 969

Table C-23. 32-Bit Opcode Instructions (Sheet 16 of 40)
Instruction
and Version
Move Register Half
Dreg_hi = A1 (IU)
Move Register Half
Dreg_lo = A0, Dreg_hi = A1 (IU)
Dreg_hi = A1, Dreg_lo = A0 (IU)
Multiply and Multiply-Accumulate to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi) (IU, M)
Vector Multiply and Multiply-Accumulate
Dreg_lo = (A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi) ,
Dreg_hi = (A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi) (IU, M)
Multiply and Multiply-Accumulate to Half Register
Dreg_hi = (A1 += Dreg_lo_hi * Dreg_lo_hi) (IU, M)
Multiply and Multiply-Accumulate to Half Register
Dreg_hi = (A1 –= Dreg_lo_hi * Dreg_lo_hi) (IU, M)
Multiply 16-Bit Operands
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi
Multiply 16-Bit Operands
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi
Multiply 16-Bit Operands
Dreg_even = Dreg_lo_hi * Dreg_lo_hi
Multiply 16-Bit Operands
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi
Vector Multiply
Dreg_even = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi
Multiply 16-Bit Operands
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (M)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (M)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Instruction Opcodes
Opcode
Range
0xC187 1800—
0xC187 19C0
0xC187 3800—
0xC187 39C0
0xC194 1800—
0xC194 D9FF
0xC194 2000—
0xC197 FFFF
0xC195 1800—
0xC195 D9FF
0xC196 1800—
0xC196 D9FF
0xC200 2000—
0xC200 27FF
0xC204 0000—
0xC204 C1FF
0xC204 2000—
0xC204 E7FF
0xC208 2000—
0xC208 27FF
0xC20C 0000—
0xC20C C1FF
0xC20C 2000—
0xC20C E7FF
0xC214 0000—
0xC214 C1FF
0xC214 2000—
0xC214 E7FF
C-169