Sic_Iwr Register - Analog Devices ADSP-BF53x Blackfin Reference

Events and Interrupts
If the default assignments shown in the System Interrupt Appendix of the
Blackfin Processor Hardware Reference for your part are acceptable, then
interrupt initialization involves only:
• Initialization of the core Event Vector Table (EVT) vector address
entries
• Initialization of the
• Unmasking the specific peripheral interrupts in
system requires

SIC_IWR Register

The System Interrupt Wakeup-Enable register (
mapping between the peripheral interrupt source and the Dynamic Power
Management Controller (DPMC). Any of the peripherals can be config-
ured to wake up the core from its idled state to process the interrupt,
simply by enabling the appropriate bit in the System Interrupt
Wakeup-enable register (
of the Blackfin Processor Hardware Reference for your part). If a peripheral
interrupt source is enabled in
causes the DPMC to initiate the core wakeup sequence in order to process
the interrupt. Note this mode of operation may add latency to interrupt
processing, depending on the power control state. For further discussion
of power modes and the idled state of the core, see the Dynamic Power
Management chapter of the Blackfin Processor Hardware Reference for your
part.
By default, as shown in the System Interrupt Appendix of the Blackfin
Processor Hardware Reference for your part, all interrupts generate a
wakeup request to the core. However, for some applications it may be
desirable to disable this function for some peripherals, such as for a
SPORTx Transmit Interrupt.
4-34 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
register
IMASK
, refer to the System Interrupt Appendix
SIC_IWR
and the core is idled, the interrupt
SIC_IWR
that the
SIC_IMASK
) provides the
SIC_IWR