Table of Contents
Advertisement
Memory Architecture
Memory Architecture
Blackfin processors have a unified 4G byte address range that spans a com-
bination of on-chip and off-chip memory and memory-mapped I/O
resources. Of this range, some of the address space is dedicated to internal,
on-chip resources. The processor populates portions of this internal mem-
ory space with:
• L1 Static Random Access Memories (SRAM)
• L2 Static Random Access Memories (SRAM)
• A set of memory-mapped registers (MMRs)
• A boot Read-Only Memory (ROM)
Figure 6-1 on page 6-3
most Blackfin processors.
Overview of On-Chip Level 1 (L1) Memory
The L1 memory system performance provides high bandwidth and low
latency. Because SRAMs provide deterministic access time and very high
throughput, DSP systems have traditionally achieved performance
improvements by providing fast SRAM on the chip.
The addition of instruction and data caches (SRAMs with cache control
hardware) provides both high performance and a simple programming
model. Caches eliminate the need to explicitly manage data movement
into and out of L1 memories. Code can be ported to or developed for the
processor quickly without requiring performance optimization for the
memory organization.
Figure 6-1
shows the typical bus architecture of single-core Blackfin
devices that do not feature L2 memories on-chip. The bus widths on the
system side may vary.
6-2
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
shows a processor memory architecture typical of
Advertisement
Table of Contents
