Analog Devices ADSP-BF53x Blackfin Reference page 934

Vector Operations Instructions
Table C-21. Vector Operations Instructions (Sheet 28 of 33)
Instruction
and Version
Vector Multiply and
Multiply-Accumulate
LEGEND:
op0 and op1 specify the arith-
metic operation for each MAC.
op0 controls MAC0 operating on
Accumulator A0 and op1 con-
trols MAC1 operating on A1.
"="
"+="
"–="
Dreg half 0 and Dreg half 1
determine which halves of the
input operand registers to use.
Dreg half 0 controls MAC0 oper-
ating on Accumulator A0 and
Dreg half 1 controls MAC1 oper-
ating on A1.
Dreg_lo * Dreg_lo
Dreg_lo * Dreg_hi
Dreg_hi * Dreg_lo
Dreg_hi * Dreg_hi
Dest. Dreg # encodes the destination Data Register.
src_reg_0 Dreg # encodes the input operand register to the left of the "*" operand.
src_reg_1 Dreg # encodes the input operand register to the right of the "*" operand.
Vector Multiply and
Multiply-Accumulate
NOTE: When issuing compatible load/store instructions in parallel with a Vector Multiply and Multi-
ply-Accumulate instruction, add 0x0800 0000 to the Vector Multiply and Multiply-Accumulate opcode.
Multiply and Multiply-Accumulate to Accumulator with Multiply and Multiply-Accumulate to Data Reg-
ister
C-134 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
op0
and
op1
0 0
0 1
1 0
Dreg
half 0
and
Dreg
half 1
0 0
0 1
1 0
1 1
Bin