Analog Devices ADSP-BF53x Blackfin Reference page 651

order versions of this instruction. By default, the low order bytes come
from the low register in the register pair. The ( – , R) option causes the
low order bytes to come from the high register.
In the optional reverse source order case (for example, using the ( – , R)
syntax), the only difference is the source registers swap places within the
register pair in their byte ordering. Assume a source register pair contains
the data shown in
Table 18-6. I-register Bits and the Byte Alignment
The bytes selected are
Two LSB's of I0 or I1
00b:
01b:
10b:
11b:
Flags Affected
None
Required Mode
User & Supervisor
Parallel Issue
This instruction can be issued in parallel with specific other 16-bit
instructions. For details, see
Example
r3 = byteop3p (r1:0, r3:2) (lo) ;
r3 = byteop3p (r1:0, r3:2) (hi) ;
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Table 18-6.
src_reg_pair_LO
byte7 byte6 byte5
byte5
byte6 byte5
"Issuing Parallel Instructions" on page
Video Pixel Operations
src_reg_pair_HI
byte4 byte3 byte2
byte3 byte2
byte4 byte3 byte2
byte4 byte3 byte2
byte4 byte3
byte1 byte0
byte1 byte0
byte1
20-1.
18-11