Analog Devices ADSP-BF53x Blackfin Reference page 774

Performance Monitoring Unit
Table 21-8. Event Monitor Table
PFMONx Fields
0x00
0x01
0x02
0x03
0x04
0x06
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x13
0x80
0x81
0x82
0x83
21-22 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Events That Cause the Count Value to Increment
Loop 0 iterations
Loop 1 iterations
Loop buffer 0 not optimized
Loop buffer 1 not optimized
PC invariant branches (requires trace buffer to be enabled, see
Register" on page 21-16)
Conditional branches
Total branches including calls, returns, branches, but not interrupts
(requires trace buffer to be enabled, see
page 21-16)
Stalls due to CSYNC, SSYNC
EXCPT instructions
CSYNC, SSYNC instructions
Committed instructions
Interrupts taken
Misaligned address violation exceptions
Stall cycles due to read after write hazards on DAG registers
Stall cycles due to RAW data hazards in computes
Code memory fetches postponed due to DMA collisions (minimum count
of two per event)
Code memory TAG stalls (cache misses, or FlushI operations, count of 3
per FlushI). Note code memory stall results in a processor stall only if
instruction assembly unit FIFO empties.
Code memory fill stalls (cacheable or non-cacheable). Note code memory
stall results in a processor stall only if instruction assembly unit FIFO emp-
ties.
Code memory 64-bit words delivered to processor instruction assembly
unit
"TBUFCTL
"TBUFCTL Register" on