Table of Contents
Advertisement
Cycle Counter
SYSCFG Register
The System Configuration register (
the processor. This register is accessible only from the Supervisor mode.
System Configuration Register (SYSCFG)
SNEN (Self-Nesting Interrupt Enable)
0 - Disable self-nesting of core
interrupts
1 - Enable self-nesting of core
interrupts
CCEN (Cycle Counter Enable)
0 - Disable 64-bit, free-running
cycle counter
1 - Enable 64-bit, free-running
cycle counter
Figure 21-15. System Configuration Register
21-26
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31 30 29 28 27 26
25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
) controls the configuration of
SYSCFG
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
1
1
0
0
0
Reset = 0x0000 0030
0
0
0
SSSTEP (Supervisor Sin-
gle Step)
When set, a Supervisor
exception is taken after each
instruction is executed. It
applies only to User mode, or
when processing interrupts in
Supervisor mode. It is
ignored if the core is pro-
cessing an exception or
higher priority event. If pre-
cise exception timing is
required, CSYNC must be
used after setting this bit.
Advertisement
Table of Contents
