Analog Devices ADSP-BF53x Blackfin Reference page 915

Table C-21. Vector Operations Instructions (Sheet 9 of 33)
Instruction
and Version
Vector Logical Shift
Dreg = Dreg >> uimm4 (V)
Vector Logical Shift
Dreg = Dreg << uimm4 (V)
Vector Logical Shift
Dreg = LSHIFT Dreg BY Dreg_lo (V)
Vector Maximum
Dreg = MAX (Dreg, Dreg) (V)
Vector Minimum
Dreg = MIN (Dreg, Dreg) (V)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (FU)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 1 1 0 1 x x 0 0 0 0 1
0xC681 8180—
0xC681 8FFF
1 0 0 0
1 1 0 0 0 1 1 0 1 x x 0 0 0 0 1
0xC681 8000—
0xC681 8E7F
1 0 0 0
1 1 0 0 0 1 1 0 0 x x 0 0 0 0 1
0xC601 8000—
0xC601 8E3F
1 0 0 0
1 1 0 0 0 1 0 x x x 0 0 0 1 1 0
0xC406 0000—
0xC406 0E3F
0 0 0 0
1 1 0 0 0 1 0 x x x 0 0 0 1 1 0
0xC406 4000—
0xC406 4E3F
0 1 0 0
1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0
0xC204 2000—
0xC204 E7FF Dreg
half 1 1 0 0
1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0
0xC284 2000—
0xC284 E7FF Dreg
half 1 1 0 0
Instruction Opcodes
Bin
Dest.
Dreg # 2's comp of uimm4
Dest.
Dreg # uimm4
Dest. Source 0
Dreg # x x x Dreg #
Dest. Source 0
Dreg # 0 0 0 Dreg #
Dest. Source 0
Dreg # 0 0 0 Dreg #
Dreg Dest. src_reg_
half 0 Dreg # 0 Dreg #
Dreg Dest. src_reg_
half 0 Dreg # 0 Dreg #
Source
Dreg #
Source
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
C-115