Analog Devices ADSP-BF53x Blackfin Reference page 707

Dual 32-Bit Operations
Dreg = Dreg + Dreg,
/* add, subtract; the set of source registers must be the same
for each operation (b) */
Dual 40-Bit Accumulator Operations
Dreg = A1 + A0,
tract Accumulators; subtract A0 from A1 (b) */
Dreg = A0 + A1,
tract Accumulators; subtract A1 from A0 (b) */
Syntax Terminology
:
Dreg R7–0
: optional
opt_mode_0
: optional
opt_mode_1
: optional
opt_mode_2
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Vector Add / Subtract instruction simultaneously adds and/or sub-
tracts two pairs of registered numbers. It then stores the results of each
operation into a separate 32-bit data register or 16-bit half register,
according to the syntax used. The destination register for each of the quad
or dual versions must be unique.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Dreg = Dreg – Dreg
Dreg = A1 – A0
Dreg = A0 – A1
, , or
(S) (CO) (SCO)
(S)
, or
(ASR) (ASL)
Vector Operations
(opt_mode_1) ;
(opt_mode_1) ;
(opt_mode_1) ;
/* add, sub-
/* add, sub-
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