Byteunpack (Quad 8-Bit Unpack) - Analog Devices ADSP-BF53x Blackfin Reference

BYTEUNPACK (Quad 8-Bit Unpack)

General Form
( dest_reg_1, dest_reg_0 ) = BYTEUNPACK src_reg_pair
( dest_reg_1, dest_reg_0 ) = BYTEUNPACK src_reg_pair (R)
Syntax
( Dreg , Dreg ) = BYTEUNPACK Dreg_pair ;
( Dreg , Dreg ) = BYTEUNPACK Dreg_pair (R) ;
order (b) */
Syntax Terminology
:
Dreg R7–0
:
Dreg_pair R1:0
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Quad 8-Bit Unpack instruction copies four contiguous bytes from a
pair of source registers, adjusting for byte alignment. The instruction
loads the selected bytes into two arbitrary data registers on half-word
alignment.
The two LSBs of the
illustrated in Table
In the default source order case (for example, not the (R) syntax), assume
the source register pair contains the data shown in
This instruction prevents exceptions that would otherwise be caused by
misaligned 32-bit memory loads issued in parallel.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
, , only
R3:2
register determine the source byte alignment, as
I0
18-31.
Video Pixel Operations
/* (b) */
/* reverse source
Table 18-31.
18-41