Analog Devices ADSP-BF53x Blackfin Reference page 666

Instruction Overview
Table 18-18. And the versions that load the result into the higher byte –
RNDH and TH – produce:
dest_reg:
Arithmetic average (or mean) is calculated by summing the four byte oper-
ands, then shifting right two places to divide by four.
When the intermediate sum is not evenly divisible by 4, precision may be
lost.
The user has two options to bias the result–truncation or biased rounding.
See "Rounding and Truncating" on page 1-19
ased rounding and truncating behavior.
The bit in the
RND_MOD
behavior of this instruction.
The only valid input source register pairs are
The Quad 8-Bit Average – Half-Word instruction provides byte align-
ment directly in the source register pairs
(typically
src_reg_1
ment in both source registers must be identical since only one register
specifies the byte alignment for them both.
The relationship between the I-register bits and the byte alignment is
illustrated in Table
In the default source order case (for example, not the (R) syntax), assume a
source register pair contains the data shown in
This instruction prevents exceptions that would otherwise be caused by
misaligned 32-bit memory loads issued in parallel.
18-26 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31................24 23................16
avg(y3, y2, z3, 0 . . . . . . 0
z2)
register has no bearing on the rounding
ASTAT
) based only on the
R3:2
18-19.
15..................8
avg(y1, y0, z1,
z0)
for a description of unbi-
and
R1:0 R3:2
(typically
src_reg_0
register. The byte align-
I0
Table 18-19.
7....................0
0 . . . . . . 0
.
) and
R1:0