Analog Devices ADSP-BF53x Blackfin Reference page 256

L1 Data Memory
CACHE CONTROL &
TO RAB
MEMORY MANAGEMENT
4 KB
4 KB
4 KB
4 KB
4 KB
LD1 32 BIT
LD0 32 BIT
STORE BUFFER
6 X 32 BIT
The shaded blocks are not present on all derivatives. For more information, please refer to the corresponding processor hardware reference.
Figure 6-10. L1 Data Memory Architecture
6-28 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
SRAM SRAM OR CACHE
CACHE
TAG
4 KB
4 KB
32 BIT
4 KB
4 KB
CACHE
TAG
CACHE
TAG
4 KB
4 KB
4 KB
4 KB
CACHE
TAG
SD 32 BIT
CACHE
TAG
HIGH PRIORITY
LINE FILL
BUFFER
4 KB
8 X 32 BIT
32 BIT
32 BIT
64 BIT
4 KB VICTIM
BUFFER
8 X 32 BIT
CACHE
TAG
CACHE
TAG
HIGH PRIORITY
LINE FILL
BUFFER
4 KB 8 X 32 BIT
32 BIT
32 BIT
32 BIT
64 BIT
4 KB VICTIM
BUFFER
8 X 32 BIT
CACHE
TAG
TO DMA CONTROLLER
TO
PROCESSOR
CORE
I/O BUFFERS
LOW PRIORITY
LINE FILL
BUFFER
8 X 32 BIT
DMA
BUFFER
HIGH PRIORITY
WRITE
BUFFER
4 X 32 BIT
LOW PRIORITY
LINE FILL
BUFFER
8 X 32 BIT
DMA
BUFFER
LOW PRIORITY
WRITE
BUFFER
2 TO 8 X 32 BIT
DCB
EAB
TO EBIU (AND L2)
READ
DMA
WRITE
READ
DMA
WRITE
16 BIT
16 BIT