Analog Devices ADSP-BF53x Blackfin Reference page 221

Table 5-1 summarizes the types of transfers and transfer sizes supported
by the addressing modes.
Table 5-1. Types of Transfers Supported and Transfer Sizes
Addressing Mode
Auto-increment
Auto-decrement
Indirect
Indexed
Post-increment
Be careful when using the
ables automatic detection of memory alignment errors. The
DISALGNEXCPT
I-register indirect addressing. Misaligned loads using P-register
addressing will still cause an exception.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Types of Transfers Transfer Sizes
Supported
To and from Data LOADS:
Registers 32-bit word
16-bit, zero extended half word
16-bit, sign extended half word
8-bit, zero extended byte
8-bit, sign extended byte
STORES:
32-bit word
16-bit half word
8-bit byte
To and from Pointer LOAD:
Registers 32-bit word
STORE:
32-bit word
To and from Data LOADS:
Registers 32-bit word
16-bit half word to Data Register high half
16-bit half word to Data Register low half
16-bit, zero extended half word
16-bit, sign extended half word
STORES:
32-bit word
16-bit half word from Data Register high half
16-bit half word from Data Register low half
DISALGNEXCPT
instruction only affects misaligned loads that use
Address Arithmetic Unit
instruction, because it dis-
5-17