Analog Devices ADSP-BF53x Blackfin Reference page 683

The four bytes, now byte aligned, are copied into the destination registers
on half-word alignment, as shown in
Table 18-33. Source Register Contains
Aligned bytes:
Table 18-34. Destination Registers Receive
dest_reg_0:
dest_reg_1:
Only register pairs
Misaligned access exceptions are disabled during this instruction.
Flags Affected
None
The ADSP-BF535 processor has fewer
operate differently than subsequent Blackfin family products. For
more information on the ADSP-BF535 status flags, see
on page
Required Mode
User & Supervisor
Parallel Issue
This instruction can be issued in parallel with specific other 16-bit
instructions. For details, see
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31................24 23................16
byte_D
31................24 23................16
and
R1:0 R3:2
A-3.
"Issuing Parallel Instructions" on page
Video Pixel Operations
Table 18-33 and
15..................8
byte_C byte_B
15..................8
byte_B
byte_D
are valid sources for this instruction.
ASTAT
Table 18-34.
7....................0
byte_A
7....................0
byte_A
byte_C
flags and some flags
Table A-1
20-1.
18-43